This invention relates to computer storage systems; more particularly it relates to a hierarchical memory system using a store-thru algorithm.
A store-thru algorithm is a technique in which data being written into the memory system by a processor is stored directly into the main memory system without first storing the data into a buffer store or cache interposed between the processor and the main memory and then transferring the data from the cache into the main memory. In such memory systems using a store-thru algorithm, it has been the practice to perform what is called a partial store operation in main memory. A partial store operation is a write operation in which only a portion of the bytes of a word stored in main memory are changed by the write command from the processor. When a partial store operation is to be performed, a number of control bits called marks are transmitted to the main memory with the write command by the processor requesting the partial store operation. There is a mark for each byte in the addressed word of data. If a byte in the word is to be changed by the write operation the mark is "1". If a byte is to remain unchanged by the write operation the mark for that byte is "0". To perform a partial store operation the word of data has to be read out of main storage into a register where the bytes represented by "1" marks are replaced by data supplied by the processor while the bytes represented by "0" marks remain unchanged. The modified word of data in the register is then rewritten back into the main memory.
A system using such a partial store operation can be found in U.S. Pat. No. 3,883,854, filed on Nov. 30, 1973 and entiled, "Interleaved Memory Control Signal And Data Handling Apparatus Using Pipelining Techniques". It can be seen in this patent that it takes longer to perform a partial store in the main memory than it does to perform a full store since the data has to be read out of main memory, modified and rewritten back into main memory. The amount of extra time it takes will vary from one computer system to another; sometimes taking twice as many processor or machine cycles to perform a partial store operation as it does to perform a full store operation. In some computer systems the number of partial stores amounts to at least half the total stores being performed in the memory.
Therefore it can be seen that the performance of partial stores degrades computer performance.
To minimize this degradation it has been suggested in U.S. Pat. No. 3,984,818, filed on Feb. 3, 1975 and entitled, "Paging In Hierarchical Memory Systems" to use the cache to assemble the changed bytes with the unchanged bytes when the word of data being addressed by the partial store operation is in the cache. This is done by interrogating the cache directory to see if the data is in the cache and, if it is, reading the data out of the cache into a register and thereafter using the marks to substitute the changed bits received from the processor. The memory words so assembled are then fed to the main memory and stored using a full store operation.
Assembly of the modified word still has to be performed by this technique. However it is performed at the operating speed of the cache which may be ten times as fast as main memory. The only operation performed at main memory speed is the full store operation. Thus a partial store operation is performed almost as fast as a full store operation using this technique.